1. Field of the Invention
This invention relates to the field of memory modules, and particularly to the output buffers of Registered Dual-Inline Memory Module (RDIMM) address registers.
2. Description of the Related Art
Dual-Inline Memory Modules (DIMMs) are the industry-standard platform on which random access memory (RAM) is provided for digital computers. Each DIMM is a printed-circuit board that contains a number of individual RAM integrated circuits (ICs) or “chips.” One variety of DIMM, called a registered DIMM (RDIMM), contains an address register that acts as an electrical buffer, distributing received memory address bits to each of the RDIMM RAM chips. RDIMMs are provided in a variety of configurations, each of which is referred to as a “raw card”. Each raw card type, as well as RAM chip and address register component, has an associated set of specifications, promulgated by the industry-supported JEDEC Solid State Technology Association international standards body. A multitude of raw card configurations exist due to the need to support different RDIMM memory capacities, as well as to support RAM chips with different internal designs, as driven by proprietary expedients that may be unique to a RAM manufacturer or manufacturing process.
One JEDEC specification details an address register that may be used on several different raw cards. One raw card type contains 9 RAM chips whose address pins are wired together in a network spanning the physical width of the RDIMM; an exemplary embodiment is shown in FIG. 1a. The other raw card types contain 18 RAM chips that are subdivided according to their placement on the RDIMM. Depending upon the logical functionality of each address bit, the address pins of the RAM chips may be wired together in groups of 4, 5, 8, or 10, in wiring networks spanning only half the physical width of the RDIMM; an exemplary embodiment of this RDIMM configuration is shown in FIG. 1b. 
To support these different raw card configurations, the address register contains an array of 28 output buffers and 28 corresponding output pins that may be organized in one of two ways. A configuration control bit applied to the address register selects between the two array deployments. As shown in FIG. 1a, the array may be organized as a 1:1 fanout array, in which 25 address bits applied as inputs are distributed to 25 of the 28 output buffers (only one buffer is shown) in 1:1 correspondence. This arrangement is specified for the raw card configuration of 9 DRAM chips wired together. Alternately, as shown in FIG. 1b, the array may be organized as a 1:2 fanout array. In this case, the array is split into two sub-arrays of 14 output buffers, denoted “A” and “B” (only two buffers are shown), with 14 address bits applied as inputs fanning out to 28 output pins through both the A and B sub-arrays. This arrangement is specified for any of the raw cards containing 18 DRAM chips, in order to support the divided wiring arrangement of the 18 chips. In order to support the 25-28 address bits required for JEDEC-standard DDR2 RDIMMs, two registers are used on an RDIMM when using registers in 1:2 fanout mode. A second configuration control bit is used to distinguish the two registers according to the specific DRAMs to which they are wired.
Conventionally, the output buffers have a unique fixed output “strength”: each buffer produces a characteristic output current and transient slew rate when driving a standardized electrical load. The output strength is engineered ad hoc for either a specific raw card configuration, or an electrical approximation that represents the mathematical average of relevant electrical dimensions of all the possible raw card configurations for which the register is intended. Address register output signal integrity degrades when the number of DRAM input pins, and/or the dimension of the wire network driven by an output buffer, differs from that for which it was designed. Signal integrity degradation can take the form of ringing, overshoot, and/or pulse reflections, all of which reduce system reliability, and impose limits on operating speed as the frequency-dependence of the actual output load amplifies the electrical loading at higher operating speed.